1. Field of the Invention
This invention relates to a TAB (Tape Automated Bonding) tape technique, and more specifically to a TAB tape technique wherein a semiconductor chip is prevented from being lifted up by the adhesion between the bonding tool and the leads at the time of lead bonding. Furthermore, this invention relates to a TAB package structure which prevents contact between the leads and the chip.
2. Description of the Related Art
TAB tape is widely used in manufacturing semiconductor integrated circuit packages. FIG. 6 schematically shows a conventional TAB tape 10, and FIG. 7 shows a sectional view along line 7--7 of FIG. 6. TAB tape 10 is comprised of an electrically insulating tape 11 of a material such as polyimide and electrically conductive leads 14 formed on the insulating tape 11. The insulating tape 11 has an opening 12 at each chip attaching position and the leads 14 are formed around opening 12. Four elongated slots 16 are formed around each opening 12. Each lead 14 has an inner lead portion 18 projecting into opening 12 and an outer lead portion 20 extending across slot 16. The outer lead portions 20 terminate in test pads 22 which are used for circuitry testing. When a semiconductor chip is attached to a TAB tape, the semiconductor chip is positioned in an opening 12, and inner lead portions 18 are connected to the pads of the chip by the use of a bonding tool called Thermode. FIG. 8 shows the lead bonding operation. In this example, tape 10 is placed so that leads 14 face downward. As shown in FIG. 8 (A), tape 10 and chip 24 are positioned so that inner lead portions 18 and electrical contact pads 26 of the chip are aligned with each other, and all the inner lead portions 18 are simultaneously thermocompressively bonded to chip pads 26 by means of bonding tool 28. The top end of the bonding tool is formed of a hard material such as sintered diamond, whereas the leads are formed of, for example, copper plated with tin. This bonding method was satisfactory when the number of leads was small, but it was found that a lift-up problem of chips could occur as the number of leads increased. When the number of leads increases, the contact area between the bonding tool and leads increases and the adhesive force between the bonding tool and leads increases. For this reason, when the bonding tool is raised after the bonding, it may happen that chip 24 is lifted up at the same time, as shown in FIG. 8 (B), making the leads deform, whereby inner lead portions 18 are brought in contact with the edge of chip 24.
Although the surface of a chip is usually covered with a surface protecting layer such as polyimide, it is not always completely covered to its edge portion. In addition, there are chips of the type in which an exposed wiring pattern for evaluating the chip characteristics is provided in the edge portion.
Accordingly, it is not desirable for the leads to touch the chip.
The above problem can be solved by adding a work step to restore the deformed leads, but such work is inefficient and also may damage the leads or chip. Alternatively, a method can be conceived in which a chip is sucked by vacuum and fixed that way at the time of bonding. However, this method is complex and expensive because it requires a vacuum control mechanism, and it also requires extra control time. Although forming the bonding tool and leads with materials which do not adhere to each other can be considered as a further method, no practical technique has been proposed.
It is preferable to ensure the prevention of contact between the leads and the chip even after the bonding. This is not ensured by the above-mentioned vacuum suction method.